It is widely known in the art that metal-oxide semiconductor (MOS) capacitors provide superior performance over other capacitor structures in integrated circuitry. One area where MOS capacitors are superior is in charge integrity when the capacitor is struck by an alpha particle. This is particularly important in dynamic random access memories(dRAMs). Alteration of the charge on the storage capacitor in a dRAM cell causes an error in the data stored. This is one form of soft error and is a widely recognized problem. MOS capacitors are less susceptible to soft errors because the alpha particle must impart MOS capacitors are less susceptible to soft errors because the alpha particle must impart enough energy to an electron to bring the electron up to the conduction band of the oxide, which is very high.
One recently developed embodiment of an MOS capacitor is the trench capacitor. This capacitor is formed by etching a cavity in the surface of a substrate (the trench), forming an insulator on the sides of the trench and filling the trench with a conductive material. One plate of the capacitor is formed by the conductive material in the trench, and the other by the substrate. In order to provide the above mentioned soft error characteristic, the charge must be stored on the inner conductive layer which is electrically isolated from the substrate by the insulator. Electrical contact to the conductive layer can be made at the top of the trench by the usual integrated circuit interconnect techniques. However, a better method for contacting the conductive layer allows the use of the upper portion of the trench for other purposes. This is one advantage of the present invention.
Another problem involving the fabrication of integrated circuitry is minimization of the surface area required for particular components. FIG. 1 is a sideview schematic diagram depicting a prior art interconnection between a first level polycrystalline silicon interconnect and the source/drain region 6 of a field effect transistor. As indicated in FIG. 2, the necessary spacing required for this interconnect is approximately 2.5 microns. One micron is required each for spacing between the interconnect and the gate and for the opening between the insulator beneath the interconnect and the source/drain region. Another 0.5 microns is required for registration errors.